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HFA3683A
TM
Data Sheet
June 2000
File Number
4634.5
2.4GHz RF/IF Converter and Synthesizer
The HFA3683A is a monolithic SiGe half-duplex RF/IF transceiver designed to operate in the 2.4GHz ISM band. The receive chain features a low noise, gain selectable amplifier (LNA) followed by a down-converter mixer. An up-converter mixer and a high performance preamplifier compose the transmit chain. The remaining circuitry comprises a high frequency Phase Locked Loop (PLL) synthesizer with a three wire programmable interface for local oscillator applications. A reduced filter count is realized by multiplexing the receive and transmit IF paths and by sharing a common differential matching network. Furthermore, both transmit and receive RF amplifiers can be directly connected to mixers. The inherent image rejection of both the transmit and receive functions allow this economic advantage. The HFA3683A is housed in a 64 lead TQFP package well suited for PCMCIA board applications.
Features
* Highly Integrated * Multiplexed RX/TX IF Path Utilizes Single IF Filter * Programmable Synthesizer * Gain Selectable LNA * Power Management/Standby Mode * Single Supply 2.7V to 3.3V Operation
Cascaded LNA/Mixer (High Gain)
* Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25dB * SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7dB * Input IP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -13dBm * IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Cascaded LNA/Mixer (Low Gain)
* Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5dB * Input P1dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5dBm * IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Ordering Information
PART NUMBER HFA3683AIN HFA3683AIN96 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 64 Ld TQFP Tape and Reel PKG. NO. Q64.10x10
Cascaded Mixer/Preamplifier
* Transmit Cascaded Mixer/Preamplifier Gain . . . . . . .25dB * SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . .10dB * Output P1dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4dBm * IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Simplified Block Diagram
RX_MX_IN RF_OUT
Applications
* IEEE802.11 1MBPS and 2MBPS Standard * Systems Targeting IEEE802.11, 11MBPS Standard * Wireless Local Area Networks
RX_MX_OUT
RX_IN
H/L
* PCMCIA Wireless Transceivers * ISM Systems * TDMA Packet Protocol Radios
CP_DO INTERFACE REF_IN TXA_OUT PLL MODULE LO_IN
TX_MX_IN
TXA_IN
2-1
TX_MX_OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
HFA3683A Pinout
HFA3683A (TQFP) TOP VIEW
GND RX_MX_IN GND TX_MX_IN+ RX_MX_OUT+ GND COL_OUT GND RF_OUT GND ITAT_RES2 BIAS2_VCC1 PTAT_RES ITAT_RES1 GND PRE_VCC1 GND LNA_VCC1 GND RX_IN GND BIAS1_VCC1 GND H/L PE2 PE1 TX_VCC1 GND TXA_OUT GND GND GND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND SYN_VCC2 GND CP_VCC2 CP_D0 GND LD TX_VCC1 GND TXA_IN GND LE DATA CLK REF_BY REF_IN RX_MX_OUTTX_MX_INGND RX_LO_DRIVER_VCC1 GND LO_VCC1 GND LO_INLO_IN+ GND TX_LO_DRIVER_VCC1 TX_MX_VCC1 TX_MX_VCC1 TX_MX_VCC1 TX_MX_OUT TX_MX_VCC1
Pin Description
PIN 2 4 6 8 9 10 11 13 17 19 21 22 23 24 NAME LNA_VCC1 RX_IN BIAS1_VCC1 H/L PE2 PE1 TX_VCC1 TXA_OUT TX_VCC1 TXA_IN LE DATA CLK REF_BY Low Noise Amplifier Positive Power Supply. Low Noise Amplifier RF Input, internally DC coupled and requires an external blocking capacitor. A shunt capacitor to ground matches the input for return loss and optimum NF. Bias Positive Power Supply for the LNA and Preamplifier. High or Low Gain Select, controls the LNA high and low gain modes. This pin along with pin PE1 and bit M(0) of PLL_PE determine which of various operational modes will be active. Please refer to the Power Enable Truth Table. This pin along with pin PE2 and bit M(0) of PLL_PE determine which of various operational modes will be active. Please refer to the Power Enable Truth Table. Transmit Amplifier Positive Power Supply, requires a high quality decoupling capacitor and a short return path. Transmit Amplifier Output, internally matched to 50, requires an external DC blocking capacitor. Transmit Amplifier Positive Power Supply. Transmit Amplifier Input, internally AC coupled. Synthesizer Latch Enable, the serial interface is active when LE is low and the serial data is latched into defined registers on the rising edge of LE. Synthesizer Serial Data Input, clocked in on the rising edge of the serial clock, MSB first. Synthesizer Clock, DATA is clocked in on the rising edge of the serial clock, MSB first. Synthesizer Reference Frequency Input Bypass, internally DC coupled and requires an external bypass to ground when REF_IN is used as a Single Ended input, alternatively, requires an external AC coupling capacitor when used as a differential input. Synthesizer Reference Frequency Input, internally DC coupled and requires an external AC coupling capacitor. DESCRIPTION
25
REF_IN
2-2
HFA3683A Pin Description
PIN 27 29 30 32 33 34 35 36 37 38 40 41 43 45 47 NAME SYN_VCC2 CP_VCC2 CP_DO LD TX_MX_VCC1 TX_MX_OUT TX_MX_VCC1 TX_MX_VCC1 TX_MX_VCC1 TX_LO_Driver_ VCC1 LO_IN+ LO_INLO_VCC1 Synthesizer Positive Power Supply. Synthesizer Charge Pump Positive Power Supply. Synthesizer Charge Pump Output, feeds the PLL loop filter. Synthesizer Lock Detect Output. Transmit Mixer Positive Power Supply. Transmit Mixer RF output, internal AC coupled and internally matched to 50. Transmit Mixer Positive Power Supply. Transmit Mixer Positive Power Supply. Transmit Mixer Positive Power Supply. Transmit LO Driver Positive Power Supply. Local Oscillator Positive Input, internally AC coupled, internally matched to 50 when the LO is driven single ended and the LO_IN- is grounded. Local Oscillator Negative Input, internally AC coupled, differential or single ended capability, ground externally for single ended operation. LO Buffer Positive Power Supply. (Continued) DESCRIPTION
RX_LO_DRIVER Receiver LO Driver Positive Power Supply. _VCC1 TX_MX_INTransmit Mixer Negative Input, internally DC coupled, high impedance input. Designed to share a common IF matching network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Receive Mixer Negative Output, open collector, high impedance output. Designed to share a common IF matching network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Receive Mixer Positive Output, open collector, high impedance output. Designed to share a common IF matching network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Transmit Mixer Positive Input, internally DC coupled, high impedance input. Designed to share a common IF matching network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing the bandwidth of the IF matching network. Receive Mixer RF Input, internally DC coupled and requires external AC coupling as well as RF matching. The recommend network consists of a 3.3pF series capacitor followed by a small series inductance of 1.4nH and then a 1.2nH shunt inductor. The series inductance is best implemented on the PC board using a narrow transmission line inductor. PLL Prescaler Positive Power Supply. Connection to external resistor sets the receive and transmit mixers tail currents, independent of Absolute Temperature. Connection to external resistor sets the receive and transmit mixers tail currents, proportional to Absolute Temperature. Bias Positive Power Supply for the receive and transmit mixers. Connection to external resistor sets the LNA and Preamplifier bias currents, independent of Absolute Temperature. Low Noise Amplifier RF Output, internally AC coupled and internally matched to 50. LNA Collector Output, requires a bypass capacitance which is resonant with the PC board parasitics. A small resistance (20) in series with the main PC board VCC buss is recommended to provide isolation from other VCC bypass capacitors. This ensures the image rejection performance of the LNA is maintained. Circuit Ground Pins (Quantity 23 each).
48
RX_MX_OUT-
49
RX_MX_OUT+
50
TX_MX_IN+
52
RX_MX_IN
54 56 57 58 59 61 63
PRE_VCC1 ITAT_RES1 PTAT_RES BIAS2_VCC1 ITAT_RES2 RF_OUT COL_OUT
All Others
GND
2-3
HFA3683A
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . . -0.3 to VCC +0.3V VCC to VCC Decouple . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Any GND to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3V Pins 4, 19, 52, 56, 57 and 59 . . . . . . . . . . . . . . . . . . . . . 0.3 to +0.6V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (TQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85oC Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
General Electrical Specifications
PARAMETER Supply Voltage Receive Total Supply Current (LNA in High Gain) Receive Total Supply Current (LNA in Low Gain) Transmit Total Supply Current Standby Total Supply Current (PLL and LO Buffers Active) TX/RX Power Down Supply Current TX/RX/Power Down Time (Note 2) RX/TX, TX/RX Switching Time (Note 2) CMOS Low Level Input Voltage (CLK, DATA, LE) (Note 3) CMOS High Level Input Voltage (CLK, DATA, LE) (Note 3) CMOS High or Low Level Input Current (CLK, DATA, LE) Control Logic Low Level Input Voltage (H/L, PE1, PE2) (Note 4) Control Logic High Level Input Voltage (H/L, PE1, PE2) (Notes 3 and 4) NOTES: 2. TX/RX/TX switching time and power Down/Up time are dependent on external components. 3. VDD is the supply voltage of external Control sources. 4. These three pins H/L, PE1 and PE2 are not connected to CMOS circuitry and have different thresholds from all other control pins. TEMP. (oC) Full 25 25 25 25 Full Full Full Full Full Full Full Full MIN 2.7 0.7VDD -3.0 -0.3 VDD-0.5 TYP 33 27 40 6 10 1 0.2 MAX 3.3 38 32 45 8 100 10 1 0.3VDD 3.6 +3.0 0.5 UNITS V mA mA mA mA A s s V V A V V
Cascaded LNA/Mixer AC Electrical Specifications
Assumes a direct connection between the LNA and Mixer, IF = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified TEMP. (oC) Full Full Full MIN 2400 280 1800 -10 21.5 -17.5 -27.5 TYP 374 -6 25 3.7 -11 -22 MAX 2500 600 2220 0 29 5.0 UNITS MHz MHz MHz dBm dB dB dBm dBm
PARAMETER RF Frequency Range IF Frequency Range LO Frequency Range LO Input Drive Level Power/Voltage Gain Noise Figure SSB Input IP3 Input P1dB
TEST CONDITIONS
Single End or Differential High Gain Mode
Full Full Full Full Full
2-4
HFA3683A
Cascaded LNA/Mixer AC Electrical Specifications
Assumes a direct connection between the LNA and Mixer, IF = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified (Continued) TEMP. (oC) Full 25 Full Full High Gain Mode Low Gain Mode LO 50 VSWR Differential IF Output Load IF Output Capacitance (Single Ended) IF Output Resistance (Single Ended) LO to Mixer RF Feedthrough (Uncascaded) LO to LNA Input Feedthrough (Cascaded, no filter) Gain Switching Speed at Full Scale - High to Low Gain Switching Speed at Full Scale - Low to High Image Rejection 1dB settling 1dB settling With Matching Network LO = Single End Shared with TX 25 25 25 25 25 25 25 25 Full Full 25 MIN -9 -42 -1 1.28 1.1:1 1.4:1 -69 TYP -5 25 -40.5 +2.5 1.65:1 1.3:1 1.4:1 200 1.2 5.5 -50 -60 0.03 0.25 14 MAX -1 -40 2.0:1 2.0:1 2.0:1 -20 -50 0.1 0.3 UNITS dB dB dBc dBm pF k dBm dBm s s dB
PARAMETER Power/Voltage Gain Noise Figure Output IM3 at -4dBm Input Tones Input P1dB LNA Input 50 VSWR
TEST CONDITIONS Low Gain Mode
Cascaded Transmit Mixer AC Electrical Specifications
Assumes a direct connection between the Mixer and Preamplifier, F = 374MHz, LO = 2075MHz at -6dBm, VCC = 2.7 Unless Otherwise Specified. TEMP. (oC) Full Full Full MIN 2400 280 1800 21 +12 +2 -10 TYP 374 25 10 +14 +4 -6 -37 -45 -15 2.3:1 1.4:1 200 1.1 0.7 MAX 2500 600 2220 29 15 +20 +9 0 -20 -30 -5 3.0:1 2.0:1 UNITS MHz MHz MHz dB dB dBm dBm dBm dBm dBm dBm pF k
PARAMETER RF Frequency Range IF Frequency Range LO Frequency Range Power Conversion Gain SSB Noise Figure Output IP3 Output P1dB LO Input Drive Level LO to Transmit Mixer RF Feedthrough (Uncascaded) LO to Transmit Amp. Output Feedthrough (Uncascaded) LO to Transmit Amp. Output Feedthrough (Cascaded, no filter) Preamplifier Output 50 VSWR LO 50 VSWR Differential IF Input Load IF Input Capacitance (Single Ended) IF Input Resistance (Single Ended)
TEST CONDITIONS
200 In, 50 Out
Full Full Full Full
Same as RX
Full 25 25 25 25
LO = Single End Shared with RX
25 25 25 25
2-5
HFA3683A
Phase Lock Loop Electrical Specifications (See Notes 5 through 13)
PARAMETER Operating LO Frequency (32/33 Prescaler) Operating LO Frequency (64/65 Prescaler) Reference Oscillator Frequency Selectable Prescaler Ratios (P) Swallow Counter Divide Ratio (A Counter) Programmable Counter Divide Ratio (B Counter) Reference Counter Divide Ratio (R Counter) Reference Oscillator Sensitivity, Single or Differential Sine Inputs Reference Oscillator Sensitivity, CMOS Inputs, Single Ended or Complimentary Reference Oscillator Duty Cycle Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Current/Tolerance Charge Pump Sink/Source Mismatch Charge Pump Output Compliance Charge Pump Supply Voltage Serial Interface Clock Width High Level tCWH Low Level tCWL Serial Interface Data/Clk Set-Up Time tCS Serial Interface Data/Clk Hold Time tCH Serial Interface Clk/LE Set-Up Time tES Serial Interface LE Pulse Width tEW NOTES: 5. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is latched into defined registers on the rising edge of LE. 6. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of the power down state without requiring the registers to be rewritten. 7. CMOS Reference Oscillator input levels are given in the General Electrical Specification section. POWER ENABLE TRUTH TABLE PE1 0 1 1 0 X NOTE: 8. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers. PE2 0 1 0 1 X PLL_PE (SERIAL BUS) 1 1 1 1 0 STATUS Power Down State, Registers in Save Mode, Inactive PLL, Active Serial Interface Receive State, Active PLL Transmit State, Active PLL Inactive Transmit and Receive States, Active PLL, Active Serial Interface Inactive PLL, Disabled PLL Registers, Active Serial Interface CMOS Inputs 250A Selection 25% 500A Selection 25% 750A Selection 25% 1mA Selection 25% TEST CONDITIONS TEMP. (oC) Full Full Full Full Full Full Full Full Full 25 25 25 25 25 Full Full Full Full Full Full Full Full Full MIN 1800 1800 32/33 0 3 3 0.5 40 0.18 0.375 0.56 0.75 0.5 2.7 20 20 20 10 20 20 TYP CMOS 0.25 0.50 0.75 1.0 MAX 2220 3500 50 64/65 127 2047 32767 VCC 60 0.32 0.625 0.94 1.25 15 VCC2 -0.5 3.6 UNITS MHz MHz MHz VPP Note 7 % mA mA mA mA % V V ns ns ns ns ns ns
2-6
HFA3683A
PLL Synthesizer Table
REGISTER DEFINITION SERIAL BITS LSB 1 R Counter A/B Counter Operational Mode 0 0 1 2 0 1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) M(0) 0 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 0 0 B(4) 0 B(5) 0 B(6) B(7)
X (Don't Care) B(8) B(9) B(10) X X
M(13) M(14) M(15)
Reference Frequency Counter/Divider
BIT R(0-14) DESCRIPTION Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down by this counter and is compared with a divided LO by a phase detector.
LO Frequency Counters/Dividers
BIT A(0-6) B(0-11) DESCRIPTION Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11-bit divider. The LO frequency is divided down by [P*B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is compared by a phase detector with the divided Reference signal.
Operational Modes
BIT M(0) M(2) M(3) M(4) DESCRIPTION (PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on. Prescaler Select. 0 = 32/33, 1 = 64/65 Charge Pump Current Setting M(4) 0 0 1 1 M(5) M(6) Charge Pump Sign M(6) 0 0 M(7) M(8) M(13) LD Pin Multiplex Operation M(13) 0 0 1 1 1 M(14) M(15) Charge Pump Operation/Test M(15) 0 0 1 1 M(5) 0 1 M(8) 0 1 0 1 1 M(14) 0 1 0 1 Normal Operation Charge Pump Constant Current Source Charge Pump Constant Current Sink High Impedance State Source Current if LO/ [P*B+A] < Ref/R Source Current if LO/ [P*B+A] > Ref/R M(7) X X X 0 1 OUTPUT AT PIN LD Lock Detect Operation Short to GND Serial Register Read Back Ref. Divided by R Waveform LO Divided by [P*B+A] Waveform OPERATION/TEST M(3) 0 1 0 1 OUTPUT SINK/SOURCE 0.25mA 0.50mA 0.75mA 1.00mA
2-7
HFA3683A
N COUNTER RESET A R COUNTER REF_IN R TO DC OFFSET CAL V ISOURCE ISINK B RESET
DUAL MODULUS CONTROL
P/P+1 PRESCALER
LO_IN+
CP_D0
VCONTROL VCO
FIGURE 1. PLL SIMPLIFIED BLOCK DIAGRAM
DATA
BIT 20: MSB
BIT 19
BIT 10
BIT 9
BIT 1
TO LO DIVIDE BY 2 DRIVERS
BIT 1: LSB
CLOCK tCWL
LE tCS OR tCH tCWH tES LE tEW
NOTES: 9. Parenthesis data indicates programmable reference divider data. 10. Data shifted into register on clock rising edge. 11. Data is shifted in MSB first. FIGURE 2. SERIAL DATA INPUT TIMING
2-8
HFA3683A
fR
fP
LD
DO
H Z
I L
I
I
fR > fP
fR = fP
fR < fP
fR < fP
fR < fP
NOTES: 12. Phase difference detection range: -2 to +2. 13. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked. FIGURE 3. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
2-9
HFA3683A Typical Evaluation Board Application
L23 C17 VCC1 C12 0.01F R11 R2 20 C3 3.9pF LNA_OUT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND TX_MX_IN+ RX_MX_OUT+ GND ITAT_RES2 BIAS2_VCC1 PTAT_RES ITAT_RES1 GND PRE_VCC1 GND COL_OUT GND RF_OUT GND RX_MX_IN 11.5K 3.3pF R12 R13 0.01F 9.53K 1.5K C25 220pF 1.2nH RX_MIX_IN
C7
C16
0.01F
L10 39nH
R15 1.1K
C14 0.01F
C2
L9 R14 39nH 1.1K
7.0pF
1 GND 2 LNA_VCC1 3 GND 4 RX_IN
VCC1 LNA_IN
RX_MX_OUT- 48 TX_MX_INGND RX_LO_DRIVER_VCC1 GND LO_VCC1 GND LO_INLO_IN+ 47 46 45 44 43 42 41 40
C4
7.0pF
C5 C1 0.5pF 0.01F C8 R3 100K LNA_H/L R4 100K PE2 R6 100K GP2 C29 100pF .01F GP1 C10 7pF R1 0
5 GND 6 BIAS1_VCC1 7 GND 8 9 10 11 12 13 H/L PE2 PE1 TX_VCC1 GND TXA_OUT
VCC1
U1 HFA3683AIN
GND 39 TX_LO_DRIVER_VCC1 38 TX_MX_VCC1 37 TX_MX_VCC1 36 TX_MX_VCC1 35 TX_MX_OUT 34 TX_MX_VCC1 33 C40 0.01F GND SYN_VCC2 GND CP_VCC2 C39 CP_D0 GND LD 0.01F R30 20K C38 0.01F
14 GND 15 GND 16 GND
100K C9 PRE_OUT 7pF PRE_IN XTAL__VCC GP4 (NO FIT) (NO FIT)
VCC1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C36 0.01F (NO FIT)
GND LE
R5
DATA CLK REF_BY REF_IN
PE1
TX_VCC1 GND TXA_IN
GP3
LD
C23 47pF
VCC2 C26 1.2pF U6 4 C54 0.1F C33 1 2 VDD ENB OUT GND F4106 3 R10 1.5K C6 L1 0.56H 22pF C19 1000pF C32 1000pF C20 100pF C22 47pF C21 R25 20K R26
20K
R8
(NO FIT) REF_IN (NO FIT)
0.1F R27 10K R28 10K R29 10K LE GND N/C UP2 UP1
C53
R16
4.7F
7pF
2-10
0
0
DATA CLK
N/C
HFA3683A Typical Evaluation Board Application (Continued)
C27
R36 IF_IN/OUT 3.3pF 0 T1
U4 4 C63 + + C51 OUT MAX8867 4.7F (NO FIT) C31 3.3pF R9 0 C34 0.01F C37 220pF C52 2 0.1F 4.7F GND SHDN BP 5 C50 0.01F C48 + IN 3
C49
VCC_IN
1
0.1F
D1
GP5
4.7F
U3 UPC2745TB C55 10pF C58 1000pF 235 4 6 1 C56 10pF R33 82 TX_MIX_OUT VCC2 C46 0.1F C47 10pF ENFVZ5F81 2 3 VCC VCONT GROUND 4 5A 5B 5C 5D RF 1 U2 R34 91 R35 82
R20 C44 VCC2 R17 2700pF 560 EXT_VCO VCC2 C62 R19 4.7F 56 C61 0.1F 4 3 OUT IN MAX8867 1 SHDN 5 BP GND 2 R21 1.74K U5 300pF C43 0.027F 3.48K C45
FILTER VALUES BW 1KHz C43 0.068F C44 0.68F R20 1.5K R21 649 C45 0.01F
(10KHz DEFAULT) 10kHz 2700pF 0.027F 3.48K 1.74K 330pF
C60 0.1F C57 0.01F C59 + 4.7F
2-11
HFA3683A Typical Performance Curves
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 2 1 3 SCALE 1dB/DIV
1
2
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
3
Marker 1 = 2.0GHz, Real = 17.6, Imaginary = 35.2 Marker 2 = 2.45GHz, Real = 18.2, Imaginary = 60.1 Marker 3 = 3.0GHz, Real = 24.6, Imaginary = 82.5 FIGURE 4. S11 LNA in HIGH GAIN
Marker 1 = 2.0GHz, 14.9dB Marker 2 = 2.45GHz, 13.4dB Marker 3 = 3.0GHz, 9.1dB FIGURE 5. S21 LNA in HIGH GAIN
SCALE 5dB/DIV 3
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
2 3 VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
1
2
1
Marker 1 = 2.0GHz, -50.3dB Marker 2 = 2.45GHz, 36.9dB Marker 3 = 3.0GHz, -32.8dB FIGURE 6. S12 LNA in HIGH GAIN
Marker 1 = 2.0GHz, Real = 25.6, Imaginary = 8.1 Marker 2 = 2.45GHz, Real = 79.5, Imaginary = -30.6 Marker 3 = 3.0GHz, Real = 17.4, Imaginary = -3.2 FIGURE 7. S22 LNA in HIGH GAIN
2-12
HFA3683A Typical Performance Curves
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 2 1 3
(Continued)
3
SCALE 2dB/DIV
1
2
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
Marker 1 = 2.0GHz, Real = 21.5, Imaginary = 42.5 Marker 2 = 2.45GHz, Real = 20.4, Imaginary = 64.0 Marker 3 = 3.0GHz, Real = 22.6, Imaginary = 87.0 FIGURE 8. S11 LOW GAIN LNA
Marker 1 = 2.0GHz, -16.4dB Marker 2 = 2.45GHz, -16.4dB Marker 3 = 3.0GHz, -17.2dB FIGURE 9. S21 LOW GAIN LNA
SCALE 5dB/DIV
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
3 3
1 2
1
2
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
Marker 1 = 2.0GHz, -16.4dB Marker 2 = 2.45GHz, 16.5dB Marker 3 = 3.0GHz, -17.6dB FIGURE 10. S12 LOW GAIN LNA
Marker 1 = 2.0GHz, Real = 29.4, Imaginary = 16.5 Marker 2 = 2.45GHz, Real = 77.7, Imaginary = 22.9 Marker 3 = 3.0, Real = 43.0, Imaginary = 21.7 FIGURE 11. S22 LOW GAIN LNA
2-13
HFA3683A Typical Performance Curves
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30dBm
(Continued)
3
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
2 2 3
1 1
Marker 1 = 2.0GHz, Real = 17.4, Imaginary = -14.8 Marker 2 = 4.5GHz, Real = 14.1, Imaginary = 9.8 Marker 3 = 3GHz, Real = 13.1, Imaginary = 33.8 FIGURE 12. S11 RX MIXER
Marker 1 = 2.0GHz, Real = 23.4, Imaginary = 5.9 Marker 2 = 2.45GHz, Real = 59.9, Imaginary = 55.7 Marker 3 = 3.0GHz, Real = 72.4, Imaginary = 12.5 FIGURE 13. S22 TX MIXER
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30dBm
SCALE 1dB/DIV 2
2 1 3
3
1
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
Marker 1 = 2.0GHz, Real = 13.2, Imaginary = 1.2 Marker 2 = 2.45GHz, Real = 11.2, Imaginary = 31.6 Marker 3 = 3.0GHz, Real = 46.6, Imaginary = 21.7 FIGURE 14. S11 PREAMP
Marker 1 = 2.0GHz, 10.7dB Marker 2 = 2.45GHz, 15.5dB Marker 3 - 3.0GHz, 12.5dB FIGURE 15. S21 PREAMP
2-14
HFA3683A Typical Performance Curves
(Continued)
SCALE 5dB/DIV
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm 3 1
3
2
2
1
VCC = 3.30V RF = 2.0GHz TO 3.0GHz ROOM TEMP Pin = -30.dBm
Marker 1 = 2.0GHz, -35.2dB Marker 2 = 2.45GHz, 30.1dB Marker 3 = 3.0GHz, -33.3dB FIGURE 16. S12 PREAMP
Marker 1 = 2.0GHz, Real = 21.9, Imaginary = 48.0 Marker 2 = 2.45GHz, Real = 53.4, Imaginary = 46.5 Marker 3 = 3.0GHz, Real = 21.4, Imaginary = 54.6 FIGURE 17. S22 PREAMP
GAIN 14.3dB AT 2.7V, 13.8dB AT 3.3V NOISE FIGURE 3.5dB AT 2.7V, 3.9dB AT 3.3V 2.7V
GAIN 16.5dB AT 2.7V, 15.7dB AT 3.3V NOISE FIGURE 2.2dB AT 2.7V, 2.7dB AT 3.3V 2.7V
3.3V
3.3V TEMP = 125oC GAIN 6dB/DIV NF 3dB/DIV TEMP = -40oC GAIN 6dB/DIV NF 3dB/DIV 3.3V
3.3V
2.7V 2.4GHz 2.5GHz
2.7V
2.4GHz
2.5GHz
FIGURE 18. LNA HIGH GAIN AND NOISE FIGURE vs SUPPLY VOLTAGE
FIGURE 19. LNA HIGH GAIN AND NOISE FIGURE vs SUPPLY VOLTAGE
2-15
HFA3683A Typical Performance Curves
GAIN -16.7dB AT 2.7V, -15.0dB AT 3.3V
(Continued)
TEMP = 125oC
GAIN -13.3dB AT 2.7V, -12.7dB AT 3.3V
TEMP = -40oC
3.3V
3.3V
2.7V
2.7V
GAIN 6dB/DIV 2.4GHz 2.5GHz
GAIN 6dB/DIV 2.4GHz 2.5GHz
FIGURE 20. LNA LOW GAIN vs SUPPLY VOLTAGE
FIGURE 21. LNA LOW GAIN vs SUPPLY VOLTAGE
GAIN AT CURSOR 7.5dB AT 2.7V, 7.6dB AT 3.3V NOISE FIGURE AT CURSOR 8.7dB AT 2.7V, 8.4dB AT 3.3V 3.3V
GAIN AT CURSOR 9.5dB AT 2.7V, 9.6dB AT 3.3V NOISE FIGURE AT CURSOR 7.0dB AT 2.7V, 6.9dB AT 3.3V 3.3V
2.7V GAIN 6dB/DIV NF 3dB/DIV 2.7V TEMP = 125oC 2.7V
2.7V TEMP = -40oC
3.3V 3.3V GAIN 6dB/DIV NF 3dB/DIV RF 2.5GHz IF 400MHz RF 2.4GHz IF 300MHz RF 2.5GHz IF 400MHz
RF 2.4GHz IF 300MHz
FIGURE 22. RX MIXER GAIN AND SSB NOISE FIGURE vs SUPPLY VOLTAGE
FIGURE 23. RX MIXER GAIN AND SSB NOISE FIGURE vs SUPPLY VOLTAGE
2-16
HFA3683A Thin Plastic Quad Flatpack Packages (TQFP)
D D1 -D-
Q64.10x10 (JEDEC MS-026ACD ISSUE B)
64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 A2 MIN 0.002 0.038 0.007 0.007 0.468 0.390 0.468 0.390 0.018 64 0.020 BSC MAX 0.047 0.005 0.041 0.010 0.009 0.476 0.397 0.476 0.397 0.029 MILLIMETERS MIN 0.05 0.95 0.17 0.17 11.90 9.9 11.9 9.9 0.45 64 0.50 BSC MAX 1.20 0.15 1.05 0.27 0.23 12.10 10.10 12.10 10.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- .
0.08 M C A-B S 0.003 DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e
-H-
4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 A2 A1
11o-13o
0.09/0.20 0.004/0.008
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
2-17

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